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INTEGRATED CIRCUITS
PCA9540 2-channel I2C multiplexer
Product specification 1999 Dec 15
Philips Semiconductors
Philips Semiconductors
Product specification
2-channel I2C multiplexer
PCA9540
FEATURES
* 1-of-2 bi-directional translating multiplexer * Channel selection via I2C bus * Operating supply voltage 2.5 to 3.6 V * Operating temperature range 0C to 70C * Power-up with all multiplexer channels deselected * Low on resistance
DESCRIPTION
The PCA9540 is a 1-of-2 bi-directional translating multiplexer, controlled via the I2C bus. The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels. Only one SCx/SDx channel is selected at a time, determined by the contents of the programmable control register. The pass gates of the multiplexer are constructed such that the VDD pin can be used to limit the maximum high voltage which will be passed by the PCA9540. This allows the use of different bus voltages on each SCx/SDx pair, so that 3.3 V parts can communicate with 5 V parts without any additional protection. External pull-up resistors can pull the bus up to the desired voltage level for this channel.
PIN CONFIGURATION
SCL SDA VDD SD0
1 2 3 4
8 7 6 5
SC1 SD1 VSS SC0
SW00491
PIN DESCRIPTION
PIN NUMBER 1 2 3 4 5 6 7 8 SYMBOL SCL SDA VDD SD0 SC0 VSS SD1 SC1 FUNCTION Serial clock line Serial data line Supply voltage Serial data 0 Serial clock 0 Supply ground Serial data 1 Serial clock 1
ORDERING INFORMATION
PACKAGES 8-Pin Plastic SO 8-Pin Plastic TSSOP TEMPERATURE RANGE 0C to +70C 0C to +70C ORDER CODE PCA9540D PCA9540PW DH DRAWING NUMBER SOT96-1 SOT505-1
1999 Dec 15
2
853-2185 22852
Philips Semiconductors
Product specification
2-channel I2C multiplexer
PCA9540
BLOCK DIAGRAM
SC0
SC1
SD0
SD1
VSS
VDD
Power-on Reset
SCL Input Filter SDA I2C-Bus Control
SW00492
1999 Dec 15
3
Philips Semiconductors
Product specification
2-channel I2C multiplexer
PCA9540
CHANNEL SELECTION
A SC0x/SD0x downstream pair, or channel, is selected by the contents of the control register. This register is written after the PCA9540 has been addressed. The 2 LSBs of the control byte are used to determine which channel is to be selected. When a channel is selected, the channel will become active after a stop condition has been placed on the I2C bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made active, so that no false conditions are generated at the time of connection. CONTROL BYTE 7 X X X 6 X X X 5 X X X 4 X X X 3 X X X 2 0 1 1 1 X 0 0 0 X 0 1 SELECTED CHANNEL none 0 (SC0/SD0) 1 (SC1/SD1)
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see FIgure 1).
SDA
CONTROL REGISTER
7 X 6 X 5 X 4 X 3 X 2 B2 1 B1 0 B0
SCL data line stable; data valid change of data allowed
SW00363
Channel select bits (read/write)
Figure 1. Bit transfer
SW00497
POWER-ON RESET
During power-up the control register defaults to all zeroes causing all the channels to be deselected.
Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 2).
System configuration
A device generating a message is a `transmitter', a device receiving is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves' (see Figure 3).
SDA
SDA
SCL S START condition P STOP condition
SCL
SW00365
Figure 2. Definition of start and stop conditions
SDA SCL
MASTER TRANSMITTER/ RECEIVER
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
I2C MULTIPLEXER
SLAVE
SW00366
Figure 3. System configuration
1999 Dec 15
4
Philips Semiconductors
Product specification
2-channel I2C multiplexer
PCA9540
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition 1 2 8 9 clock pulse for acknowledgement
SW00368
Figure 4. Acknowledgement on the
slave address
I2C-bus
1
1
1
0
0
0
0
fixed
hardware selectable
SW00564
Figure 5. Slave address
SDA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SLAVE ADDRESS
CONTROL REGISTER
SDA
S
1
1
1
0
0
0
0
0 R/W
A
X
X
X
X
X
B2
B1
B0
A
P
start condition
acknowledge from slave
acknowledge from slave
PREVIOUS CHANNEL tpv
NEW CHANNEL
SW00498
Figure 6. WRITE control register
SLAVE ADDRESS CONTROL REGISTER last byte
SDA
S
1
1
1
0
0
0
0
1 R/W
A
X
X
X
X
X
B2
B1
B0
NA
P stop condition
start condition
acknowledge from slave
no acknowledge from master
SW00499
Figure 7. READ control register
1999 Dec 15
5
Philips Semiconductors
Product specification
2-channel I2C multiplexer
PCA9540
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).Voltages are referenced to GND (ground = 0 V). SYMBOL VDD VI II IO IDD ISS Ptot Tstg Tamb PARAMETER DC supply voltage DC input voltage DC input current DC output current Supply current Supply current total power dissipation Storage temperature range Operating ambient temperature CONDITIONS RATING -0.5 to +7.0 -0.5 to +7.0 20 25 100 100 400 -60 to +150 0 to +70 UNIT V V mA mA mA mA mW C C
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C.
DC CHARACTERISTICS
VDD = 2.5 to 3.6 V; VSS = 0 V; Tamb = 0C to +70C; unless otherwise specified. SYMBOL Supply VDDQn VDD IDD IDP Istb VPOR Supply voltage Supply current Power on current Standby current Power-on reset voltage Operating mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 100 kHz Power on mode with no channels selected Standby mode; VDD = 3.6 V; no load; VI = VDD or VSS VDD = 3.6 V; no load; VI = VDD or VSS 2.5 - - - - 20 140 2.5 1.3 3.6 100 200 100 2.1 V A A A V PARAMETER TEST CONDITIONS LIMITS MIN TYP MAX UNIT
Input SCL; input/output SDA VIL VIH IO OL IL Ci VIL VIH ILI Pass Gate RO ON Switch resistance VCC = 3.67 V, VO = 0.4 V, IO = 15 mA VCC = 2.3 to 2.7 V, VO = 0.4 V, IO = 10 mA Vswin = VDD = 3.3 V; Iswout = -100 A VP Pass Switch output voltage out ut Vswin = VDD = 3.0 to 3.6 V; Iswout = -100 A Vswin = VDD = 2.5 V; Iswout = -100 A Vswin = VDD = 2.3 to 2.7 V; Iswout = -100 A 1.1 1.6 1.5 2.0 5 7 20 26 2.2 2.8 V 21 55 LOW level input voltage HIGH level input voltage LOW level output current Leakage current Input capacitance LOW level input voltage HIGH level input voltage Input leakage current pin at VDD or VSS VOL = 0.4 V VOL = 0.6 V VI = VDD or VSS VI = VSS -0.5 0.3 VDD 3 6 -1 - -0.5 0.7 VDD -1 - - - - - - - - - 0.3 VDD 6 - - +1 10 +0.3 VDD VDD + 0.5 +1 V V mA mA A pF V V A
Select inputs A0 to A2 / INT0 to INT3
1999 Dec 15
6
Philips Semiconductors
Product specification
2-channel I2C multiplexer
PCA9540
AC CHARACTERISTICS
SYMBOL tpd fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tSU:STO tr tf Cb PARAMETER Propagation delay from SDA to SDn or SCL to SCn SCL clock frequency Bus free time between a STOP and START condition Hold time (repeated) START condition After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time: for CBUS compatible masters for I2C-bus devices Data set-up time Set-up time for STOP condition Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Capacitive load for each bus line 0 4.7 4.0 4.7 4.0 4.7 5.0 02 250 - - 4.0 STANDARD-MODE I2C-BUS MIN MAX 0.31 100 - - - - - - - - 1000 300 - 400 0 1.3 0.6 1.3 0.6 0.6 - 02 1004 20 + 0.1Cb 0.6 -
5
FAST-MODE I2C-BUS MIN MAX 0.31 400 - - - -
UNIT ns kHz s s s s s
- 0.93 - 300 300 - 400
s s ns ns ns s pF
20 + 0.1Cb5
NOTES: 1. Pass gate propagation delay is calculated from the 20 typical RON and and the 15 pF load capacitance. 2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 3. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. 4. A fast-mode I2C bus device can be used in a standard-mode I2C-bus system, but the requirement tSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU:DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line is released. 5. Cb = total capacitance of one bus line in pF.
SDA
tBUF
tLOW
tR
tF
tHD;STA
tSP
SCL
tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr
tSU;STA
tSU;STO P
SU00645
Figure 8. Definition of timing on the
I2C-bus
1999 Dec 15
7
Philips Semiconductors
Product specification
2-channel I2C multiplexer
PCA9540
SO8: plastic small outline package; 8 leads; body width 3.9mm
SOT96-1
1999 Dec 15
8
Philips Semiconductors
Product specification
2-channel I2C multiplexer
PCA9540
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
1999 Dec 15
9
Philips Semiconductors
Product specification
2-channel I2C multiplexer
PCA9540
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 02-00 Document order number: 9397 750 06882
Philips Semiconductors
1999 Dec 15 10

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